Abstract: High-performance computing plays a key role in supporting the advancement of modern and emerging high-power applications. With the advent of 2.5D and 3D packaging solutions, systems that consume tens of kilowatts of power become viable. Considering the high current and power density requirements in these systems, the path forward with traditional power delivery approaches is, however, unsustainable with respect to energy efficiency and thermal challenges. In response to these challenges, vertical power delivery has emerged as a promising solution to address the unprecedented power loss in high-performance computing systems at the package level. With this approach, high power is distributed through package-level networks at low current and converted with power-efficient converters close to the functional dies/chiplets. As a result, the distribution of high-current power is limited to short vertical interconnect between the converters and points-of-load, mitigating power loss and thermal challenges. While vertical power delivery is a promising approach to manage high-current high-density power, distribution of the active and passive power converter components around the periphery and on the backside of functional dies/chiplets and efficient conversion of power within limited footprint near points-of-load are topics of active research. Package-to-die power delivery architectures and design methodologies, power circuits for efficient power conversion, and vertically-stacked, highly dense and efficient passive components are the key for enabling high-performance computing. This talk will explore these challenges in detail and investigate ways to mitigate them in the context of high-performance computing.
About the Speaker: Inna Partin-Vaisband is an Assistant Professor of Electrical and Computer Engineering and holds an appointment as a Courtesy Assistant Professor of Computer Science at the University of Illinois Chicago. She received the B.Sc. in computer science and M.Sc. in electrical engineering from the Technion-Israel Institute of Technology, Haifa, Israel, in, respectively, 2006 and 2009, and the Ph.D. degree in electrical engineering from the University of Rochester, Rochester, New York, in 2015. Between 2003 and 2009, Inna held a variety of software and hardware R&D positions at Tower Semiconductor Ltd., G-Connect Ltd., and IBM Ltd. She is an Associate Editor of the Microelectronics Journal. Her research is currently focused on innovation in the areas of chiplets, power delivery and management, hardware security, and electronic design automation. Her research into heterogeneous power delivery and management has been published in her book On-Chip Power Delivery and Management, 4th Edition. A distributed system of ultra-small on-chip power supplies previously designed, fabricated, and tested by her was in mass production within the Galaxy android smart phones as part of the Qualcomm Snapdragon product line. Inna is leading the power delivery effort in the JUMP 2.0 Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES) and the heterogeneous integration effort in the JUMP 2.0 Center on Cognitive Multispectral Sensors (CogniSense). She is the recipient of the 2022 Google Research Scholar Award and the 2023 NSF CAREER Award.
Contact Person: Dr. Richard Xian-Ke GAO, A*STAR Institute of High Performance Computing; E-mail: [email protected]