As the feature size of silicon-based integrated circuits (ICs) approaches the physical limit, short-channel effects appear, gate control attenuates, and leakage current increases, which seriously affects transistor performance and causes chip failure [1]. Due to the inherent thickness of bulk silicon, the physical area cannot be further reduced, which restricts the area efficiency of silicon- based ICs [2]. In addition, the speed mismatch between memory readout and logic operation [3], and the separation of memory and computing units together form the memory wall bottleneck in silicon-based ICs. With unique characteristics, including no dangling bond surface, atomic-level thickness, abundant adjustable energy bands, excellent optical electrostatic properties etc. [4], two-dimensional (2D) materials have the potential to enhance gate control, reduce leakage, improve energy and area efficiency, and realize the integration of perception, memory and computing. This report discusses the roadmap for the fusion of 2D materials and silicon ICs, including alleviating the problems faced by silicon ICs from the application of 2D materials in gate-all-around, memory and logic transistors, and enabling the creation of an all-in-one sensing, memory and computing system. Finally, it provides an outlook on the challenges and promising paths to fusing 2D materials with silicon ICs for large-scale applications.
[1] Nat. Nano., 15, 545-557 (2020). [2] Nat. Nano., 14, 662-667 (2019).
[3] Nat. Nano., 13, 404-410 (2018). [4] Nat. Nano., 9, 768-779 (2014).