Seminar Abstract:

In this talk, I will highlight some of our recent research findings. The research is divided into two parts. The first part deals with designing integrated wireless power transfer receiver for biomedical implants, and the second part deals with solving critical issues in semiconductor memory.

For the first part of the research, we recognize that wireless power transfer (WPT) through an inductive link can provide convenient and reliable power to implantable medical devices (IMDs) for biomedical applications. The WPT system consists of a power transmitter and a power receiver. The power receiver consists of a secondary coil in parallel with a resonating capacitor. For a conventional design, the parallel-resonant circuit drives a rectifier that converts the AC voltage to DC voltage, and the rectifier is then cascaded with a voltage regulator to provide a stable DC voltage for supplying power to downstream electronics. The research focuses on the design of the power receiver in reducing the reverse current of the rectifier and enhancing the power conversion efficiency (PCE). The resonant frequency is chosen to be 40.68 MHz to minimize the size of the secondary coil, and all integrated circuits are designed using 0.13-μm CMOS processes. First, a digital-control on-off delay-compensated 40.68 MHz full[1]wave active rectifier is proposed. It consists of two NMOS active diodes and a cross-coupled PMOS transistor pair. High efficiency is achieved by eliminating turn-on delay, reverse current, and multiple pulsing using digital techniques. The measured maximum voltage conversion ratio (VCR) is 0.97, and the measured maximum PCE is 93.2% for a 500 Ω load resistance. Second, an on-off delay-compensated 40.68 MHz active full-wave rectifier with an embedded voltage-doubler is proposed. A conventional full-wave rectifier consists of four diodes, yet the proposed full-wave rectifier with embedded voltage-doubler consists of only two active diodes, with one using a PMOS and the other an NMOS power transistor. The measured maximum VCR is 1.91, and the maximum PCE is 91.9% for a load resistance of 200 Ω. Third, a 40.68 MHz one-stage 2X/0X reconfigurable resonant regulating (R3 ) rectifier is proposed. AC to DC rectification and voltage regulation are achieved in one stage using only two power MOS transistors. Mode-switching is realized through PWM control, and Type-II compensation is used to achieve fast transient response. The output voltage is regulated at 1.2 V. The measured PCE reaches up to 90.7%. The measured undershoot and overshoot are lower than 95 mV, and the settling time is less than 25 μs when the load switches between 1.2 mA and 12 mA.

The second part of the research focuses on solving critical issues in semiconductor memory. Among several memory technologies, static random access memory (SRAM) is considered to be the most suitable choice for cache memory because of its high-speed operations. The most commonly used SRAM is the standard 6T cell. However, the standard 6T SRAM cell shows poor read and/or write ability and also consumes high hold power. Therefore, first, we present a stable differential SRAM cell for low-power applications. The proposed cell has a similar structure to the standard 6T SRAM cell with the addition of two buffer transistors, one tail transistor, and one complimentary word line. Due to the stacking effect, the proposed cell consumes low power. The impact of process parameter variations on various design metrics of the proposed cell was investigated and compared with that of 6T and of 8T cells. Following this, we focused on solving the half-select issue in SRAM cells. In this regard, we presented some novel SRAM cells that support a bit-interleaving architecture so that the half-select issue is eliminated. Additionally, we worked on improving the other important design metrics of an SRAM cell, such as the read stability, write ability, and hold power. We further extended our research on designing radiation-hardened SRAM for space applications. In space, if a voltage pulse (generated due to radiation particles striking the integrated circuit) is larger than the switching threshold of the logic circuit, data at the sensitive node may get flipped, leading to a single-event upset (SEU). The research focuses on the design of radiation-hardened circuits for memory cells. Due to positive feedback in a conventional 6T SRAM cell, a change in the state of one storage node (due to SEU) causes the other storage node to change, ultimately flipping the state of the cell. Hence, the traditional SRAM cell should be modified such that it can retain its state even if the stored data get flipped by an SEU or SEMNU (single[1]event multi-node upset). Therefore, we proposed some novel SRAM cells that can fully recover from SEUs of both polarities induced at any single sensitive node. The proposed cells also address the issue of the single-event multi[1]node upset as they exhibit soft-error recovery at the affected node-pair.

About the Speaker:

SOUMITRA PAL received the M.E. degree in Electronics and Communication Engineering from the Birla Institute of Technology, Ranchi, India, in 2015, and the Ph.D. degree in Electronic and Computer Engineering from The Hong Kong University of Science and Technology (HKUST), Hong Kong, in 2021. He worked as a Postdoctoral Scholar with the Department of Electronic and Computer Engineering, HKUST, from September 2021 to February 2022 and with the Department of Electrical and Computer Engineering at the University of California, Los Angeles, from April 2022 to August 2023. Since September 2023, he has been working as an R&D Engineer, Sr I, in Synopsys Inc., Sunnyvale, California. He is the author or co-author of more than 40 research articles. His research interests include designing semiconductor memory, power management circuits and systems, and wireless power transfer circuits and systems. Dr. Pal was a recipient of the Graduate Aptitude Test in Engineering (GATE) Scholarship from the All India Council for Technical Education (AICTE), Government of India, from 2013 to 2015, and the HKUST Postgraduate Studentship, from 2016 to 2021. He received the IET Circuits, Devices and Systems Premium Award for two consecutive years, 2020 and 2021, and the Best Paper Award at the Third International Conference on Information System Design and Intelligent Applications, in 2016. He has served as a guest associate editor for Frontiers in Electronics for the Power Electronics section. Dr. Pal has also served as a reviewer for multiple international journals/conferences.


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