Abstract:The rapid progress of AI is creating an urgent demand for new hardware, yet chip design remains slow, expensive, and deeply human-intensive. This tension is forcing both academia and industry to rethink the future of Electronic Design Automation (EDA): how far can AI move beyond isolated tool assistance, and what would it take for AI systems to reason across larger parts of the design flow? This talk will discuss this question through three technical challenges at the intersection of AI and hardware design. First, chip design is inherently multimodal, while today’s large language models still struggle to perceive and reason over these heterogeneous representations. Second, chip design remains a problem of extreme scale, where optimization must handle complex physical constraints and combinatorial spaces across increasingly large systems. Third, as AI infrastructure grows, hardware reliability becomes a first-order concern: escaped defects, weak fault models, and silent data corruption can undermine the correctness of large-scale training and inference systems. Wei Li will present his research toward addressing these challenges, including graph and language-model-based representations for chip data, differentiable solvers for EDA tasks, and testing and diagnosis methods for robust AI hardware. The talk will conclude with a discussion of open challenges and future opportunities in EDA and testing.

Bio: Wei LI is an assistant professor in the School of Computing at the National University of Singapore (NUS). He obtains his Ph.D. degree at Carnegie Mellon University, advised by Prof. José Moura and Prof. Shawn Blanton. Before joining CMU, he received his Bachelor (ELITE STREAM) and MPhil degrees from CUHK, CSE Department, advised by Prof. Bei Yu. Wei was named a 2026 ML and Systems Rising Star. He is a recipient of the Croucher Fellowship, the Apple Ph.D. Fellowship in Integrated Systems twice, and the Qualcomm Innovation Fellowship. His research has received Best Paper Awards at ASP-DAC, ISSTA, and ICTAI, as well as a Best Paper Honorable Mention at ICLAD. His work spans EDA, hardware testing, and AI for chip design. His research has demonstrated industrial impact through collaborations with Qualcomm, Intel, Google, and Broadcom; algorithms integrated into Apple’s industrial physical design flows; and a joint patent filing with NVIDIA on differentiable global routing.