A workshop on VLSI Design Using Cadence EDA Tools was held on 8th July 2013 in VLSI Lab, Dept of EEE, BUET. The event was jointly organized by Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology (BUET), IEEE EDS/SSCS Bangladesh Chapter and IEEE GOLD Affinity Group Bangladesh Chapter. Due to the limitation on the number of licenses of the Cadence EDA toos, total number of participants were limited. The participants had to pre-register for the event. A total 15 (fifteen) IEEE Members attended the workshop, where 11 are members of IEEE GOLD Affinity Group Bangladesh Chapter.
The workshop started at 10.00 AM. IEEE GOLD Bangladesh Chair, Sajid Muhaimin Choudhury introduced the speakers at the beginning. Chair of IEEE EDS/SSCS Bangladesh Chapter, Prof. ABM Harun-ur Rashid conducted the first session. He gave basic idea on CMOS technology, fabrication process and design flow and design flow. Afterwards Shah Md. Abid Hussain, Lecturer, United International University, conducted the Tutorial sessions. Participants were given hands on training to effectively create and edit schematics for use with the full suite of Cadence® simulation and layout tools. Participant created the schematic of a macro cell using Virtuoso Schematic editor L, created symbol and performed Spectre simulation to verify functionality of the cell. In the evening session layout of the macro cell was created, Design rule was check, Layout Versus Schematic was done and post Layout simulation including parasitic extraction was performed.
The daylong workshop included two light refreshments and a lunch for all registered participants. At the end of the workshop, Chair of IEEE Bangladesh Section, Prof. Pran Kanai Saha distributed certificates among the participants and gave a concluding speech, thanking the participants and the organizers. The event concluded at 5.00 PM.