It will be a half day workshop consisting of two segments. In the starting segment Prof. Dr. A.B.M. Harun-ur Rashid will give an opening speech on importance and future prospect of VLSI ASIC
design and its academic exclusiveness in Bangladesh. In the next segment Mr. Sazadur Rahman will conduct an interactive workshop on RTL synthesis, Physical Design and Verification of a simple ASIC chip using Cadence Genus RTL Synthesis, Cadence Innovus Implementation and Cadence Virtuoso. Attendees will get to access Cadence tools and get a hands on experience on RTL to GDSII design flow. Each step will be briefly discussed first and then attendees will get to run those steps by themselves in the workshop.

Speaker 1:
Dr. A.B.M. Harun-ur Rashid
Professor, Department of EEE
Bangladesh University of Engineering and Technology (BUET)
Dr. Harun is considered as the pioneer of VLSI in Bangladesh who has led this field in BUET for more than 20 years and taken up to international level. By this time Dr. Harun has brought about significant upgradation of VLSI related courses, led researches not only in BUET but also in other private organizations. Earlier he has completed PhD degree from The University of Tokyo, Japan after completion of BSc from the department of EEE, BUET. Upon completion of PhD Dr. Harun has served Texas Instruments, Japan for 5 years as Design Engineer and developed Bi-CMOS which was used by TI in many AMS chips. He has also served as a visiting research fellow at Hiroshima University. As a very talented student and energetic researcher Dr. Harun received several prestigious domestic and international awards, honors & scholarships.

Speaker 2:
Sazadur Rahman
Senior Design Engineer
Neural Semiconductor Ltd, DBL Group
Sazadur Rahman, a young IC design engineer has finished his undergrad from the department of Electrical and Electronic Engineering, BUET with a major in electronics. Starting his career as a Physical Design Engineer at PrimeSilicon Technology (BD) Ltd., Sazadur Rahman has worked in cutting edge IC design technology in TSMC 28nm & Samsung 2.5D FinFET 14nm node where he has contributed in 4 successful Tapeouts. As an enthusiast engineer Sazadur had the privilege of working in 28nm highspeed router chip, data center chip, Samsung HBM Gen2 PHY high performance-high bandwidth memory. Throughout the period Sazadur gathered expertise in most of the EDA tools from Cadence, Synopsys, Mentor Graphics and AtopTech. Currently Sazadur is serving as a Senior Design Engineer at Neural Semiconductor Ltd where he is leading the Physical Design team.